SMJ320C6414 Datasheet, PDF (97/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUTx
CEx
ABE[7:0] or BBE[1:0]
AEA[22:14] or BEA[20:12]
AEA[12:3] or BEA[10:1]
AEA13 or BEA11
ACTV
1
1
4
5
Bank Activate
4
5
Row Address
4
5
Row Address
AED[63:0] or BED[15:0]
AOE/SDRAS/SOE‡
12
12
ARE/SDCAS/SADS/SRE‡
AWE/SDWE/SWE‡
† _{These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a}
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
‡ _{ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM}
accesses.
Figure 29. SDRAM ACTV Command for EMIFA and EMFB^†
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