SMJ320C6414 Datasheet, PDF (95/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ
ECLKOUTx
CEx
ABE[7:0] or BBE[1:0]
1
1
2
3
BE1
BE2
BE3
BE4
AEA[22:14] or BEA[20:12]
AEA[12:3] or BEA[10:1]
4
5
Bank
4
5
Column
AEA13 or BEA11
AED[63:0] or BED[15:0]
4
5
6
7
D1
D2
D3
D4
AOE/SDRAS/SOE‡
ARE/SDCAS/SADS/SRE‡
8
8
AWE/SDWE/SWE‡
PDT§
14
14
† _{These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a}
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
‡ _{ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM}
accesses.
§ _{PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data}
is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a read transaction. The latency of the PDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11,
respectively. PDTRL equals 00 (zero latency) in Figure 27.
Figure 27. SDRAM Read Command (CAS Latency 3) for EMIFA and EMIFB^†
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