SMJ320C6414 Datasheet, PDF (48/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
EMIFB (16-bit) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY^||k
BCE3
BCE2
BCE1
BCE0
D11
O/Z
IPU
C9
O/Z
IPU ^{EMIFB memory space enables}
• Enabled by bits 26 through 31 of the word address
H12
O/Z
IPU _{• Only one pin is asserted during any external data access}
G12
O/Z
IPU
BBE1
BBE0
EMIFB byte-enable control
D12
O/Z
IPU _{• Decoded from the low-order address bits. The number of address bits or byte enables}
used depends on the width of external memory.
E12
O/Z
IPU ^{• Byte-write enables for most types of memory}
• Can be directly connected to SDRAM read and write mask signal (SDQM)
BPDT
E11
O/Z
IPU EMIFB peripheral data transfer, allows direct transfer between external peripherals
EMIFB (16-BIT) − BUS ARBITRATION^||k
BHOLDA
F12
O
IPU EMIFB hold-request-acknowledge to the host
BHOLD
C19
I
IPU EMIFB hold request from the host
BBUSREQ
D14
O
IPU EMIFB bus request output
EMIFB (16-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL^||k
BECLKIN
EMIFB external input clock. The EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock)
E10
I
IPD is selected at reset via the pullup/pulldown resistors on the BEA[15:14] pins.
BECLKIN is the default for the EMIFB input clock.
BECLKOUT2
EMIFB output clock 2. Programmable to be EMIFB input clock (BECLKIN, CPU/4 clock, or
C8
O/Z
IPD _{CPU/6 clock) frequency divided by 1, 2, or 4.}
BECLKOUT1
J12
O/Z
IPD
EMIFB output clock 1 [at EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
EMIFB asynchronous memory read-enable/SDRAM column-address strobe/programmable
BARE/
BSDCAS/
BSADS/BSRE
C7
O/Z
synchronous interface-address strobe or read-enable
IPU
• For programmable synchronous interface, the RENEN field in the CE Space Secondary
Control Register (CExSEC) selects between BSADS and BSRE:
If RENEN = 0, then the BSADS/BSRE signal functions as the BSADS signal.
If RENEN = 1, then the BSADS/BSRE signal functions as the BSRE signal.
BAOE/
BSDRAS/
BSOE
D10
O/Z
IPU
EMIFB asynchronous memory output-enable/SDRAM row-address strobe/programmable
synchronous interface output-enable
BAWE/BSDWE/
BSWE
F11
O/Z
IPU
EMIFB asynchronous memory write-enable/SDRAM write-enable/programmable synchro-
nous interface write-enable
BSOE3
J13
O/Z
IPU EMIFB synchronous memory output enable for BCE3 (for glueless FIFO interface)
BARDY
G11
I
IPU EMIFB asynchronous memory ready input
† _{I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground}
‡ _{IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite}
supply rail, a 1-kΩ resistor should be used.)
|| _{These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal}
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
kTo maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
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