SMJ320C6414 Datasheet, PDF (105/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
RESET TIMING
timing requirements for reset^† (see Figure 37)
NO.
MIN MAX UNIT
1 tw(RST)
Width of the RESET pulse (PLL stable)‡
Width of the RESET pulse (PLL needs to sync up)§
10P*
ns
250*
µs
16 tsu(boot)
17 th(boot)
Setup time, boot configuration bits valid before RESET high¶
Hold time, boot configuration bits valid after RESET high¶
4P*
ns
4P*
ns
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
‡ _{This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x6, x12 when CLKIN and PLL are stable.}
§ _{This parameter applies to CLKMODE x6, x12 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock}
PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During
that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.
¶ _{EMIFB address pins BEA[20:13, 11, 7] are the boot configuration pins during device reset.}
switching characteristics over recommended operating conditions during reset^†#|| (see Figure 37)
NO.
PARAMETER
MIN
MAX UNIT
2 td(RSTL-ECKI)
Delay time, RESET low to ECLKIN synchronized internally
2E* 3P + 20E* ns
3 td(RSTH-ECKI)
Delay time, RESET high to ECLKIN synchronized internally
2E* 8P + 20E* ns
4 td(RSTL-ECKO1HZ) Delay time, RESET low to ECLKOUT1 high impedance
2E*
ns
5 td(RSTH-ECKO1V)
Delay time, RESET high to ECLKOUT1 valid
8P + 20E* ns
6 td(RSTL-EMIFZHZ)
Delay time, RESET low to EMIF Z high impedance
2E* 3P + 4E* ns
7 td(RSTH-EMIFZV)
Delay time, RESET high to EMIF Z valid
16E* 8P + 20E* ns
8 td(RSTL-EMIFHIV)
Delay time, RESET low to EMIF high group invalid
2E*
ns
9 td(RSTH-EMIFHV)
Delay time, RESET high to EMIF high group valid
8P + 20E* ns
10 td(RSTL-EMIFLIV)
Delay time, RESET low to EMIF low group invalid
2E*
ns
11 td(RSTH-EMIFLV)
Delay time, RESET high to EMIF low group valid
8P + 20E* ns
12 td(RSTL-LOWIV)
Delay time, RESET low to low group invalid
0*
ns
13 td(RSTH-LOWV)
Delay time, RESET high to low group valid
11P* ns
14 td(RSTL-ZHZ)
Delay time, RESET low to Z group high impedance
0*
ns
15 td(RSTH-ZV)
Delay time, RESET high to Z group valid
2P*
8P* ns
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
# _{E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.}
|| _{EMIF Z group consists of: AEA[22:3], BEA[20:1], AED[63:0], BED[15:0], CE[3:0], ABE[7:0], BBE[1:0], ARE/SDCAS/SADS/SRE,}
AWE/SDWE/SWE, and AOE/SDRAS/SOE, SOE3, ASDCKE, and PDT.
EMIF high group consists of: AHOLDA and BHOLDA (when the corresponding HOLD input is high)
EMIF low group consists of: ABUSREQ and BBUSREQ; AHOLDA and BHOLDA (when the corresponding HOLD input is low)
Low group consists of:
XSP_CS, CLKX2/XSP_CLK, and DX2/XSP_DO; all of which apply only when PCI EEPROM (BEA13)
is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and DX2/XSP_DO
pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section
of this data sheet.
Z group consists of:
HD[31:0]/AD[31:0], CLKX0, CLKX1/URADDR4, CLKX2/XSP_CLK, FSX0, FSX1/UXADDR3, FSX2, DX0,
DX1/UXADDR4, DX2/XSP_DO, CLKR0, CLKR1/URADDR2, CLKR2, FSR0, FSR1/UXADDR2, FSR2,
TOUT0, TOUT1, TOUT2, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP13/PINTA,
GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP,
HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, UXDATA[7:0], UXSOC, UXCLAV,
and URCLAV.
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