SMJ320C6414 Datasheet, PDF (102/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
AECLKOUTx
ACEx
≥ TRAS cycles
Self Refresh
End Self-Refresh
ABE[7:0]
AEA[22:14, 12:3]
AEA13
AED[63:0]
AAOE/ASDRAS/ASOE‡
AARE/ASDCAS/ASADS/
ASRE‡
AAWE/ASDWE/ASWE‡
13
13
ASDCKE
† _{These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a}
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
‡ _{AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,}
respectively, during SDRAM accesses.
Figure 34. SDRAM Self-Refresh Timing for EMIFA Only^†
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