SMJ320C6414 Datasheet, PDF (89/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
timing requirements for programmable synchronous interface cycles for EMIFB module^†
(see Figure 24)
NO.
MIN MAX UNIT
6 tsu(EDV-EKOxH) Setup time, read EDx valid before ECLKOUTx high
3.1
ns
7 th(EKOxH-EDV)
Hold time, read EDx valid after ECLKOUTx high
1.5
ns
† _{These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a}
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable
synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for
EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
switching characteristics over recommended operating conditions for programmable
synchronous interface cycles for EMIFB module^†‡ (see Figure 24−Figure 26)
NO.
PARAMETER
MIN MAX UNIT
1 td(EKOxH-CEV)
Delay time, ECLKOUTx high to CEx valid
1.3 6.4 ns
2 td(EKOxH-BEV)
Delay time, ECLKOUTx high to BEx valid
6.4 ns
3 td(EKOxH-BEIV)
Delay time, ECLKOUTx high to BEx invalid
1.3
ns
4 td(EKOxH-EAV)
Delay time, ECLKOUTx high to EAx valid
6.4 ns
5 td(EKOxH-EAIV)
Delay time, ECLKOUTx high to EAx invalid
1.3
ns
8 td(EKOxH-ADSV)
Delay time, ECLKOUTx high to SADS/SRE valid
1.3 6.4 ns
9 td(EKOxH-OEV)
Delay time, ECLKOUTx high to, SOE valid
1.3 6.4 ns
10 td(EKOxH-EDV)
Delay time, ECLKOUTx high to EDx valid
6.4 ns
11 td(EKOxH-EDIV)
Delay time, ECLKOUTx high to EDx invalid
1.3
ns
12 td(EKOxH-WEV)
Delay time, ECLKOUTx high to SWE valid
1.3 6.4 ns
† _{These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a}
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable
synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for
EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
‡ _{The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):}
− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
− CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).
− Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).
− Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
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