SMJ320C6414 Datasheet, PDF (82/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
INPUT AND OUTPUT CLOCKS (CONTINUED)
timing requirements for ECLKIN for EMIFA and EMIFB^{†‡§} (see Figure 19)
NO.
MIN MAX UNIT
1 tc(EKI)
Cycle time, ECLKIN
6¶* 16P* ns
2 tw(EKIH) Pulse duration, ECLKIN high
2.7*
ns
3 tw(EKIL)
Pulse duration, ECLKIN low
2.7*
ns
4 tt(EKI)
Transition time, ECLKIN
2* ns
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
‡ _{The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.}
§ _{These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are}
prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.
¶ _{Minimum ECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements.}
On the 7E3 and 6E3 devices, 133-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. On the 5E0 devices,
100-MHz operation is achievable if the requirements of the EMIF Device Speed section are met.
ECLKIN
1
4
2
3
4
Figure 19. ECLKIN Timing for EMIFA and EMIFB
switching characteristics over recommended operating conditions for ECLKOUT1 for EMIFA and
EMIFB modules^§#||k (see Figure 20)
NO.
PARAMETER
MIN
MAX UNIT
1 tJ(EKO1)
Period jitter, ECLKOUT1
0* ±175^h* ps
2 tw(EKO1H)
Pulse duration, ECLKOUT1 high
EH − 0.7* EH + 0.7* ns
3 tw(EKO1L)
Pulse duration, ECLKOUT1 low
EL − 0.7* EL + 0.7* ns
4 tt(EKO1)
Transition time, ECLKOUT1
1* ns
5 td(EKIH-EKO1H) Delay time, ECLKIN high to ECLKOUT1 high
1*
8* ns
6 td(EKIL-EKO1L) Delay time, ECLKIN low to ECLKOUT1 low
1*
8* ns
*This parameter is not production tested.
§ _{These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are}
prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.
# _{The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.}
|| _{E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.}
kEH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA or EMIFB.
hThis period jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
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