SMJ320C6414 Datasheet, PDF (44/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only]
(CONTINUED)
PCBE0
Y3
I/O/Z
PCI command/byte enable 0 (I/O/Z). When PCI is disabled (PCI_EN = 0), this pin is tied-off.
For the C6414 device this pin is “Reserved (leave unconnected, do not connect to power or
ground).”
XSP_CS
PCI serial interface chip select (O). When PCI is disabled (PCI_EN = 0), this pin is tied-off.
AA3
O
IPD For the C6414 device this pin is “Reserved (leave unconnected, do not connect to power or
ground).”
CLKX2/
XSP_CLK§
W5
I/O/Z
IPD McBSP2 transmit clock (I/O/Z) [default] or PCI serial interface clock (O).
DR2/XSP_DI§
Y4
I
IPU
McBSP2 receive data (I) [default] or PCI serial interface data in (I). In PCI mode, this pin is
connected to the output data pin of the serial PROM.
DX2/XSP_DO§
GP15/PRST§
GP14/PCLK§
GP13/PINTA§
GP12/PGNT§
GP11/PREQ§
GP10/PCBE3§
GP9/PIDSEL§
McBSP2 transmit data (O/Z) [default] or PCI serial interface data out (O). In PCI mode, this pin
R9
O/Z
IPU _{is connected to the input data pin of the serial PROM.}
J8
General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default.
G5
GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default.
G4
GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default.
J7
I/O/Z
H6
GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default.
GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default.
L7
GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.
K6
GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default.
EMIFA (64-bit) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY^||k
ACE3
ACE2
ACE1
ACE0
K20
O/Z
IPU
L17
O/Z
IPU ^{EMIFA memory space enables}
• Enabled by bits 28 through 31 of the word address
J21
O/Z
IPU _{• Only one pin is asserted during any external data access}
K19
O/Z
IPU
ABE7
P19
O/Z
IPU
ABE6
U22
O/Z
IPU
ABE5
ABE4
ABE3
ABE2
T22
O/Z
IPU EMIFA byte-enable control
R21
O/Z
IPU ^{• Decoded from the low-order address bits. The number of address bits or byte enables}
used depends on the width of external memory.
M17
O/Z
IPU _{• Byte-write enables for most types of memory}
M18
O/Z
IPU • Can be directly connected to SDRAM read and write mask signal (SDQM)
ABE1
H22
O/Z
IPU
ABE0
L19
O/Z
IPU
APDT
L20
O/Z
IPU EMIFA peripheral data transfer, allows direct transfer between external peripherals
† _{I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground}
‡ _{IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite}
supply rail, a 1-kΩ resistor should be used.)
§ _{For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.}
The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions
for this device.
|| _{These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal}
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
kTo maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
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