SMJ320C6414 Datasheet, PDF (126/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
UTOPIA SLAVE TIMING [C6415 AND C6416 ONLY] (CONTINUED)
timing requirements for UTOPIA Slave receive (see Figure 60)
NO.
1 tsu(URDV-URCH)
2 th(URCH-URDV)
3 tsu(URAV-URCH)
4 th(URCH-URAV)
Setup time, URDATA valid before URCLK high
Hold time, URDATA valid after URCLK high
Setup time, URADDR valid before URCLK high
Hold time, URADDR valid after URCLK high
9 tsu(URENBL-URCH) Setup time, URENB low before URCLK high
10 th(URCH-URENBL) Hold time, URENB low after URCLK high
11 tsu(URSH-URCH) Setup time, URSOC high before URCLK high
12 th(URCH-URSH)
Hold time, URSOC high after URCLK high
MIN MAX UNIT
4
ns
1
ns
4
ns
1
ns
4
ns
1
ns
4
ns
1
ns
switching characteristics over recommended operating conditions for UTOPIA Slave receive
(see Figure 60)
NO.
PARAMETER
5 td(URCH-URCLAV)
Delay time, URCLK high to URCLAV driven active value
6 td(URCH-URCLAVL)
Delay time, URCLK high to URCLAV driven inactive low
7 td(URCH-URCLAVHZ)
Delay time, URCLK high to URCLAV going Hi-Z
8 tw(URCLAVL-URCLAVHZ) Pulse duration (low), URCLAV low to URCLAV Hi-Z
*This parameter is not production tested.
MIN
MAX UNIT
3
12 ns
3*
12* ns
9*
18.5* ns
3*
ns
URCLK
URDATA[7:0]
2
1
P48
H1
H2
H3
URADDR[4:0] N
0x1F
URCLAV
N
3
N+1
4
0x1F
5
N+1
N+2
7
8
6
0x1F
N+2
URENB
10
9
URSOC
11
12
† The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and
URSOC signals).
Figure 60. UTOPIA Slave Receive Timing^†
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