SMJ320C6414 Datasheet, PDF (116/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING
timing requirements for McBSP^† (see Figure 51)
NO.
2 tc(CKRX)
3 tw(CKRX)
5 tsu(FRH-CKRL)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Setup time, external FSR high before CLKR low
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
MIN
6.67‡*
0.5tc(CKRX)−1§*
9
1.3
MAX
UNIT
ns
ns
ns
CLKR int
6
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low
CLKR ext
3
ns
CLKR int
8
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low
CLKR ext
0.9
ns
CLKR int
3
8 th(CKRL-DRV) Hold time, DR valid after CLKR low
CLKR ext
3.1
ns
CLKX int
9
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low
CLKX ext
1.3
ns
CLKX int
6
11 th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX ext
3
ns
*This parameter is not production tested.
† _{CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.}
‡ _{Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and ac timing}
requirements.
§ _{This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.}
116
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