SMJ320C6414 Datasheet, PDF (7/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
functional block and CPU (DSP core) diagram
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
VCP†
SDRAM
SBSRAM
ZBT SRAM
FIFO
TCP†
64
EMIF A
16
EMIF B
Timer 2
SRAM
ROM/FLASH
Timer 1
I/O Devices
Timer 0
McBSP2
UTOPIA:
Up to 400 Mbps
Master ATMC
McBSPs:
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
UTOPIA‡
or
McBSP1‡
Enhanced
DMA
Controller
(64-channel)
L2
Memory
1024K
Bytes
McBSP0
C64x Digital Signal Processor
L1P Cache
Direct-Mapped
16K Bytes Total
C64x DSP Core
Instruction Fetch
Instruction Dispatch
Advanced Instruction Packet
Instruction Decode
Data Path A
Data Path B
A Register File
A31−A16
A15−A0
B Register File
B31−B16
B15−B0
Control
Registers
Control
Logic
Test
Advanced
In-Circuit
Emulation
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
Interrupt
Control
L1D Cache
2-Way Set-Associative
16K Bytes Total
16
GPIO[8:0]
GPIO[15:9]‡
32
HPI‡
or
PCI‡
Interrupt
Selector
PLL
(x1, x6, x12)
Power-Down
Logic
Boot Configuration
† _{VCP and TCP decoder coprocessors are applicable to the C6416 device only.}
‡ _{For the C6415 and C6416 devices, the UTOPIA peripheral is MUXed with McBSP1, and the PCI peripheral is MUXed with the HPI}
peripheral and the GPIO[15:9] port. For more details on the multiplexed pins of these peripherals, see the Device Configurations section
of this data sheet.
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