SMJ320C6414 Datasheet, PDF (80/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN^{†‡§} (see Figure 16)
PLL MODE x12 PLL MODE x6
NO.
MIN MAX
MIN MAX
1 tc(CLKIN) Cycle time, CLKIN
20 33.3 13.3 33.3
2 tw(CLKINH) Pulse duration, CLKIN high
0.4C*
0.4C*
3 tw(CLKINL) Pulse duration, CLKIN low
0.4C*
0.4C*
4 tt(CLKIN) Transition time, CLKIN
5*
5*
*This parameter is not production tested.
† _{The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.}
‡ _{For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.}
§ _{C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.}
x1 (BYPASS)
MIN MAX
13.3* 33.3
0.45C*
0.45C*
1*
UNIT
ns
ns
ns
ns
CLKIN
1
4
2
3
4
Figure 16. CLKIN Timing
80
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