SMJ320C6414 Datasheet, PDF (71/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
power-down mode logic
Figure 8 shows the power-down mode logic on the C6414/C6415/C6416.
CLKOUT4 CLKOUT6
Internal Clock Tree
PD1
Clock
Distribution
and Dividers
PD2
Clock
PLL
Power-
Down
Logic
IFR
IER
PWRD ^CSR
CPU
Internal
Peripherals
PD3
SMJ320C6414/15/16
CLKIN
RESET
† _{External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic.}
Figure 8. Power-Down Mode Logic^†
triggering, wake-up, and effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 9 and described in Table 33.
When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when
writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU
and Instruction Set Reference Guide (literature number SPRU189).
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