SMJ320C6414 Datasheet, PDF (83/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
INPUT AND OUTPUT CLOCKS (CONTINUED)
ECLKIN
Ideal Clock Period
ECLKOUT1
5
1
6
3
2
4
4
Figure 20. ECLKOUT1 Timing for EMIFA and EMIFB Modules
switching characteristics over recommended operating conditions for ECLKOUT2 for the EMIFA
and EMIFB modules^{†‡§} (see Figure 21)
NO.
PARAMETER
MIN
MAX UNIT
1 tJ(EKO2)
Period jitter, ECLKOUT2
0*
±175¶* ps
2 tw(EKO2H) Pulse duration, ECLKOUT2 high
0.5NE − 0.7* 0.5NE + 0.7* ns
3 tw(EKO2L)
Pulse duration, ECLKOUT2 low
0.5NE − 0.7* 0.5NE + 0.7* ns
4 tt(EKO2)
Transition time, ECLKOUT2
1*
ns
5 td(EKIH-EKO2H) Delay time, ECLKIN high to ECLKOUT2 high
1*
8*
ns
6 td(EKIH-EKO2L) Delay time, ECLKIN high to ECLKOUT2 low
1*
8*
ns
*This parameter is not production tested.
† _{The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.}
‡ _{These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are}
prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.
§ _{E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.}
N = the EMIF input clock divider; N = 1, 2, or 4.
¶ _{This period jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.}
5
6
ECLKIN
Ideal Clock Period
ECLKOUT2
1
3
2
4
4
Figure 21. ECLKOUT2 Timing for the EMIFA and EMIFB Modules
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