SMJ320C6414 Datasheet, PDF (93/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles for EMIFA module^† (see Figure 27)
NO.
MIN MAX UNIT
6 tsu(EDV-EKO1H) Setup time, read EDx valid before ECLKOUTx high
0.6
ns
7 th(EKO1H-EDV) Hold time, read EDx valid after ECLKOUTx high
1.8
ns
† _{These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a}
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
switching characteristics over recommended operating conditions for synchronous DRAM cycles
for EMIFA module^† (see Figure 27−Figure 34)
NO.
PARAMETER
MIN MAX UNIT
1 td(EKO1H-CEV)
Delay time, ECLKOUTx high to CEx valid
2 td(EKO1H-BEV)
Delay time, ECLKOUTx high to BEx valid
3 td(EKO1H-BEIV)
Delay time, ECLKOUTx high to BEx invalid
4 td(EKO1H-EAV)
Delay time, ECLKOUTx high to EAx valid
5 td(EKO1H-EAIV)
Delay time, ECLKOUTx high to EAx invalid
8 td(EKO1H-CASV)
Delay time, ECLKOUTx high to SDCAS valid
9 td(EKO1H-EDV)
Delay time, ECLKOUTx high to EDx valid
10 td(EKO1H-EDIV)
Delay time, ECLKOUTx high to EDx invalid
11 td(EKO1H-WEV)
Delay time, ECLKOUTx high to SDWE valid
12 td(EKO1H-RAS)
Delay time, ECLKOUTx high to SDRAS valid
13 td(EKO1H-ACKEV) Delay time, ECLKOUTx high to ASDCKE valid (EMIFA only)
1.3 4.9 ns
4.9 ns
1.3
ns
4.9 ns
1.3
ns
1.3 4.9 ns
4.9 ns
1.3
ns
1.3 4.9 ns
1.3 4.9 ns
1.3 4.9 ns
14 td(EKO1H-PDTV)
Delay time, ECLKOUTx high to PDT valid
1.3 4.9 ns
† _{These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a}
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
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