SMJ320C6414 Datasheet, PDF (75/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
bootmode
The C6414/15/16 device resets using the active-low signal RESET. While RESET is low, the device is held in
reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and
states of device pins during reset. The release of RESET starts the processor running with the prescribed device
configuration and boot mode.
The C6414/C6415/C6416 has three types of boot modes:
D Host boot
If host boot is selected, upon release of RESET, the CPU is internally “stalled” while the remainder of the
device is released. During this period, an external host can initialize the CPU’s memory space as necessary
through the host interface, including internal configuration registers, such as those that control the EMIF or
other peripherals. For the C6414 device, the HPI peripheral is used for host boot. For the C6415/C6416
device, the HPI peripheral is used for host boot if PCI_EN = 0, and the PCI peripheral is used for host boot if
PCI_EN = 1. Once the host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC
register to complete the boot process. This transition causes the boot configuration logic to bring the CPU
out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT condition is not
latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT brings the CPU
out of the “stalled” state only if the host boot process is selected. All memory may be written to and read by
the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is out of the
“stalled” state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
D EMIF boot (using default ROM timings)
Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0
by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be stored
in the endian format that the system is using. In this case, the EMIF automatically assembles consecutive
8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA
as a single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU
is released from the “stalled” state and starts running from address 0.
D No boot
With no boot, the CPU begins direct execution from the memory located at address 0. Note: operation is
undefined if invalid code is located at address 0.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
75