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SMJ320C6414 Datasheet, PDF (77/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS | |||
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SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDÄPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A â JANUARY 2004 â REVISED MARCH 2004
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONSâ
MIN
TYP
MAX
UNIT
VOH High-level output voltage (except PCI) DVDD = MIN,
IOH = MAX
2.4
V
High-level output voltage (PCI)
VOHP [C6415/C6416 only]
IOHP = â0.5 mA,
DVDD = 3.3 V
0.9DVDD¶
V
VOL
VOLP
Low-level output voltage (except PCI)
Low-level output voltage (PCI)
[C6415/C6416 only]
DVDD = MIN,
IOLP = 1.5 mA,
IOL = MAX
DVDD = 3.3 V
0.4
V
0.1DVDD¶
V
VI = VSS to DVDD no opposing internal
resistor
±10
uA
II
Input current (except PCI)
VI = VSS to DVDD opposing internal
pullup resistorâ¡
50
100
150
uA
VI = VSS to DVDD opposing internal
pulldown resistorâ¡
â150 â100
â50
uA
Input leakage current (PCI)
IIP
[C6415/C6416 only]§
0 < VIP < DVDD = 3.3 V
±10
uA
EMIF, CLKOUT4, CLKOUT6, EMUx
â16
mA
IOH High-level output current
Timer, UTOPIA, TDO, GPIO (Excluding
GP[15:9, 2, 1]), McBSP
PCI/HPI
â8
mA
â0.5¶
mA
EMIF, CLKOUT4, CLKOUT6, EMUx
16
mA
IOL Low-level output current
Timer, UTOPIA, TDO, GPIO (Excluding
GP[15:9, 2, 1]), McBSP
PCI/HPI
8
mA
1.5¶
mA
IOZ
ICDD
IDDD
Off-state output current
Core supply current#
I/O supply current#
VO = DVDD or 0 V
CVDD = 1.4 V, CPU clock = 600 MHz
DVDD = 3.3 V, CPU clock = 600 MHz
±10
uA
750
mA
125
mA
Ci
Input capacitance
12
pF
Co
Output capacitance
12
pF
â For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
â¡ Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
§ PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.
¶ These rated numbers are from the PCI specification version 2.3. The DC specification and AC specification are defined in Tables 4-3 and 4-4,
respectively.
# Measured with average activity (50% high/50% low power). The actual current draw is highly application-dependent. For more details on core
and I/O activity, refer to the TMS320C6414/15/16 Power Consumption Summary application report (literature number SPRA811).
recommended clock and control signal transition behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
⢠POST OFFICE BOX 1443 HOUSTON, TEXAS 77251â1443
77
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