SMJ320C6414 Datasheet, PDF (31/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

signal groups description (continued)
64
AED[63:0]
ACE3
ACE2
ACE1
ACE0
20
AEA[22:3]
ABE7
ABE6
ABE5
ABE4
ABE3
ABE2
ABE1
ABE0
Data
Memory Map
Space Select
Address
Byte Enables
BED[15:0]
BCE3
BCE2
BCE1
BCE0
BEA[20:1]
BBE1
BBE0
16
Data
Memory Map
Space Select
20
Address
Byte Enables
EMIFB (16-bit)†
SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
External
Memory I/F
Control
Bus
Arbitration
EMIFA (64-bit)†
External
Memory I/F
Control
Bus
Arbitration
AECLKIN
AECLKOUT1
AECLKOUT2
ASDCKE
AARE/ASDCAS/ASADS/ASRE
AAOE/ASDRAS/ASOE
AAWE/ASDWE/ASWE
AARDY
ASOE3
APDT
AHOLD
AHOLDA
ABUSREQ
BECLKIN
BECLKOUT1
BECLKOUT2
BARE/BSDCAS/BSADS/BSRE
BAOE/BSDRAS/BSOE
BAWE/BSDWE/BSWE
BARDY
BSOE3
BPDT
BHOLD
BHOLDA
BBUSREQ
† _{These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is}
an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document,
in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name.
Figure 3. Peripheral Signals
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31