SMJ320C6414 Datasheet, PDF (113/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415 AND C6416 ONLY]
timing requirements for PCLK^†‡ (see Figure 47)
NO.
MIN
1 tc(PCLK)
Cycle time, PCLK
30 (or 8P§)*
2 tw(PCLKH) Pulse duration, PCLK high
11*
3 tw(PCLKL) Pulse duration, PCLK low
11*
4 tsr(PCLK)
∆v/∆t slew rate, PCLK
1*
*This parameter is not production tested.
† _{For 3.3-V operation, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN.}
‡ _{P = 1/CPU clock frequency in ns. For example when running parts at 600 MHz, use P = 1.67 ns.}
§ _{Select the parameter value of 30 ns or 8P, whichever is greater.}
MAX
4*
UNIT
ns
ns
ns
V/ns
PCLK
1
4
2
3
4
Figure 47. PCLK Timing
0.4 DVDD V MIN
Peak to Peak for
3.3V signaling
timing requirements for PCI reset (see Figure 48)
NO.
1 tw(PRST)
Pulse duration, PRST
2 tsu(PCLKA-PRSTH) Setup time, PCLK active before PRST high
*This parameter is not production tested.
PCLK
PRST
1
2
Figure 48. PCI Reset (PRST) Timing
MIN
1*
100*
MAX
UNIT
ms
µs
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