SMJ320C6414 Datasheet, PDF (103/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles for EMIFA and EMIFB modules^† (see Figure 35)
NO.
3 toh(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low
*This parameter is not production tested.
† _{E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.}
MIN MAX
E*
UNIT
ns
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles
for EMIFA and EMIFB modules^{†‡§} (see Figure 35)
NO.
PARAMETER
MIN MAX UNIT
1 td(HOLDL-EMHZ)
Delay time, HOLD low to EMIF Bus high impedance
2E*
¶* _ns
2 td(EMHZ-HOLDAL)
Delay time, EMIF Bus high impedance to HOLDA low
0* 2E* ns
4 td(HOLDH-EMLZ)
Delay time, HOLD high to EMIF Bus low impedance
2E* 7E* ns
5 td(EMLZ-HOLDAH)
6 td(HOLDL-EKOHZ)
Delay time, EMIF Bus low impedance to HOLDA high
Delay time, HOLD low to ECLKOUTx high impedance
0* 2E* ns
2E*
¶* _ns
7 td(HOLDH-EKOLZ)
Delay time, HOLD high to ECLKOUTx low impedance
2E* 7E* ns
*This parameter is not production tested.
† _{E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.}
‡ _{For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and}
AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.
For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE, BAOE/BSDRAS/BSOE, and
BAWE/BSDWE/BSWE, BSOE3, and BPDT.
§ _{The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,}
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35.
¶ _{All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay}
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
HOLD
HOLDA
EMIF Bus†
2
1
C64x
3
5
4
C64x
ECLKOUTx‡
(EKxHZ = 0)
6
7
ECLKOUTx‡
(EKxHZ = 1)
† _{For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and}
AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT.
For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE, BAOE/BSDRAS/BSOE, and
BAWE/BSDWE/BSWE, BSOE3, and BPDT.
‡ _{The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,}
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35.
Figure 35. HOLD/HOLDA Timing for EMIFA and EMIFB
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