SMJ320C6414 Datasheet, PDF (117/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP^†‡ (see Figure 51)
NO.
PARAMETER
MIN
MAX UNIT
1
td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated
from CLKS input
2 tc(CKRX)
3 tw(CKRX)
4 td(CKRH-FRV)
9 td(CKXH-FXV)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
1.4
10 ns
6.67§*
ns
C − 1¶* C + 1¶* ns
−2.1
3 ns
−1.7
3
ns
1.7
9
Disable time, DX high impedance following last data bit
12 tdis(CKXH-DXHZ) _{from CLKX high}
13 td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX int
CLKX ext
CLKX int
CLKX ext
−3.9*
−2.1*
4*
ns
9*
−3.9 + D1# 4 + D2#
−2.1 + D1# 9 + D2#
ns
Delay time, FSX high to DX valid
FSX int
−2.3
5.6
14 td(FXH-DXV)
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
ns
1.9
9
*This parameter is not production tested.
† _{CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.}
‡ _{Minimum delay times also represent minimum output hold times.}
§ _{Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing}
requirements.
¶ _{C = H or L}
S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).
# _{Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.}
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
117