SMJ320C6414 Datasheet, PDF (123/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1^†‡ (see Figure 56)
MASTER
SLAVE
NO.
MIN MAX
MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high
12*
5 th(CKXH-DRV) Hold time, DR valid after CLKX high
4*
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
‡ _{For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.}
2 − 12P*
5 + 24P*
UNIT
ns
ns
switching characteristics over recommended operating conditions for McBSP as SPI Master or
Slave: CLKSTP = 11b, CLKXP = 1^†‡ (see Figure 56)
NO.
1 th(CKXH-FXL)
2 td(FXL-CKXL)
3 td(CKXH-DXV)
6 tdis(CKXH-DXHZ)
PARAMETER
Hold time, FSX low after CLKX high¶
Delay time, FSX low to CLKX low#
Delay time, CLKX high to DX valid
Disable time, DX high impedance following last data bit
from CLKX high
MASTER§
MIN MAX
H − 2* H + 3*
T − 2* T + 1*
−2*
4*
SLAVE
MIN
MAX
12P + 4* 20P + 17*
UNIT
ns
ns
ns
−2*
4* 12P + 3* 20P + 17* ns
7 td(FXL-DXV)
Delay time, FSX low to DX valid
L − 2* L + 4* 8P + 2* 16P + 17* ns
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
‡ _{For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.}
§ _{S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)}
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ _{FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX}
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
# _{FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock}
(CLKX).
CLKX
1
FSX
6
DX
Bit 0
DR
Bit 0
2
7
Bit(n-1)
4
Bit(n-1)
3
(n-2)
5
(n-2)
(n-3)
(n-4)
(n-3)
(n-4)
Figure 56. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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