SMJ320C6414 Datasheet, PDF (41/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
SIGNAL
NAME
NO.
CLKIN
H4
CLKOUT4/GP1§ Y7
CLKOUT6/GP2§ T10
CLKMODE1
K8
CLKMODE0
E3
PLLV¶
L9
TMS
TDO
TDI
TCK
TRST
EMU11
EMU10
EMU9
EMU8
EMU7
EMU6
EMU5
EMU4
EMU3
EMU2
V14
W16
AA17
Y15
Y14
V15
Y16
T14
U14
AB18
AA16
W15
AB17
W14
AA15
EMU1
T13
EMU0
V13
TYPE†
I
I/O/Z
I/O/Z
I
I
A#
I
O/Z
I
I
I
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD/
IPU‡
IPD
IPD
IPD
IPD
IPD
IPU
IPU
IPU
IPU
IPD
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
Terminal Functions
DESCRIPTION
CLOCK/PLL CONFIGURATION
Clock Input. This clock is the input to the on-chip PLL.
Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a
GPIO 1 pin (I/O/Z).
Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a
GPIO 2 pin (I/O/Z).
Clock mode select
• Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x6, or x12.
For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL
section of this data sheet.
PLL voltage supply
JTAG EMULATION
JTAG test-port mode select
JTAG test-port data out
JTAG test-port data in
JTAG test-port clock
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG
Compatibility Statement section of this data sheet.
Emulation pin 11. Reserved for future use, leave unconnected.
Emulation pin 10. Reserved for future use, leave unconnected.
Emulation pin 9. Reserved for future use, leave unconnected.
Emulation pin 8. Reserved for future use, leave unconnected.
Emulation pin 7. Reserved for future use, leave unconnected.
Emulation pin 6. Reserved for future use, leave unconnected.
Emulation pin 5. Reserved for future use, leave unconnected.
Emulation pin 4. Reserved for future use, leave unconnected.
Emulation pin 3. Reserved for future use, leave unconnected.
Emulation pin 2. Reserved for future use, leave unconnected.
Emulation [1:0] pins
• Select the device functional mode of operation
EMU[1:0]
Operation
00
Boundary Scan/Normal Mode (see Note)
01
Reserved
10
Reserved
11
Emulation/Normal Mode [default] (see the IEEE 1149.1 JTAG
Compatibility Statement section of this data sheet)
Normal mode refers to the DSPs normal operational mode, when the DSP is free running. The
DSP can be placed in normal operational mode when the EMU[1:0] pins are configured for
either Boundary Scan or Emulation.
Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the internal pulldown
(IPD) on the TRST signal must not be opposed in order to operate in Normal mode.
For the Boundary Scan mode pulldown EMU[1:0] pins with a dedicated 1-kΩ resister.
† _{I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground}
‡ _{IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite}
supply rail, a 1-kΩ resistor should be used.)
§ _{These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.}
¶ _{PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.}
# _{A = Analog signal (PLL Filter)}
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