SMJ320C6414 Datasheet, PDF (108/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
HOST-PORT INTERFACE (HPI) TIMING
timing requirements for host-port interface cycles^†‡ (see Figure 39 through Figure 46)
NO.
1 tsu(SELV-HSTBL)
2 th(HSTBL-SELV)
3 tw(HSTBL)
4 tw(HSTBH)
10 tsu(SELV-HASL)
11 th(HASL-SELV)
12 tsu(HDV-HSTBH)
13 th(HSTBH-HDV)
14 th(HRDYL-HSTBL)
Setup time, select signals§ valid before HSTROBE low
Hold time, select signals§ valid after HSTROBE low
Pulse duration, HSTROBE low
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals§ valid before HAS low
Hold time, select signals§ valid after HAS low
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
MIN
5
2.4
4P¶*
4P*
5
2
5
2.8
2*
18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low
2
19 th(HSTBL-HASL)
Hold time, HAS low after HSTROBE low
2.1
*This parameter is not production tested.
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
§ _{Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.}
¶ _{Select the parameter value of 4P or 12.5 ns, whichever is greater.}
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
switching characteristics over recommended operating conditions during host-port interface
cycles^†‡ (see Figure 39 through Figure 46)
NO.
PARAMETER
6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high#
7
td(HSTBL-HDLZ)
Delay time, HSTROBE low to HD low impedance for an
HPI read
MIN
MAX UNIT
1.3 4P + 8
ns
2*
ns
8 td(HDV-HRDYL) Delay time, HD valid to HRDY low
−3
ns
9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high
1.5
ns
15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance
12*
ns
16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid (HPI16 only)
4P + 8
ns
*This parameter is not production tested.
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
# _{This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16)}
on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until
the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is
full.
108
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443