SMJ320C6414 Datasheet, PDF (45/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
NAME
NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
EMIFA (64-BIT) − BUS ARBITRATION^||k
AHOLDA
M19
O
IPU EMIFA hold-request-acknowledge to the host
AHOLD
U21
I
IPU EMIFA hold request from the host
ABUSREQ
P21
O
IPU EMIFA bus request output
EMIFA (64-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL^||k
AECLKIN
EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock)
J19
I
IPD is selected at reset via the pullup/pulldown resistors on the BEA[17:16] pins.
AECLKIN is the default for the EMIFA input clock.
AECLKOUT2
K18
O/Z
IPD
EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock, or
CPU/6 clock) frequency divided-by-1, -2, or -4.
AECLKOUT1
H21
O/Z
IPD
EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
EMIFA asynchronous memory read-enable/SDRAM column-address strobe/programmable
AARE/
ASDCAS/
ASADS/ASRE
L16
O/Z
synchronous interface-address strobe or read-enable
IPU
• For programmable synchronous interface, the RENEN field in the CE Space Secondary
Control Register (CExSEC) selects between ASADS and ASRE:
If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal.
If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal.
AAOE/
ASDRAS/
ASOE
J20
O/Z
IPU
EMIFA asynchronous memory output-enable/SDRAM row-address strobe/programmable
synchronous interface output-enable
AAWE/
ASDWE/
ASWE
G22
O/Z
IPU
EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable synchro-
nous interface write-enable
ASDCKE
K21
O/Z
IPU
EMIFA SDRAM clock-enable (used for self-refresh mode). [EMIFA module only.]
• If SDRAM is not in system, ASDCKE can be used as a general-purpose output.
ASOE3
N16
O/Z
IPU EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface)
AARDY
L18
I
IPU Asynchronous memory ready input
EMIFA (64-BIT) − ADDRESS^||k
AEA22
R20
AEA21
P16
AEA20
T20
AEA19
R18
AEA18
V22
AEA17
AEA16
R19
O/Z
IPD EMIFA external address (doubleword address)
T21
AEA15
P17
AEA14
N18
AEA13
P18
AEA12
P20
AEA11
N17
† _{I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground}
‡ _{IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite}
supply rail, a 1-kΩ resistor should be used.)
|| _{These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal}
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
kTo maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
45