SMJ320C6414 Datasheet, PDF (119/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 52)
NO.
1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high
2 th(CKSH-FRH) Hold time, FSR high after CLKS high
*This parameter is not production tested.
MIN MAX UNIT
4*
ns
4*
ns
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
1
2
Figure 52. FSR Timing When GSYNC = 1
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0^†‡ (see Figure 53)
MASTER
NO.
MIN MAX
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low
12
5 th(CKXL-DRV) Hold time, DR valid after CLKX low
4
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
‡ _{For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.}
SLAVE
MIN MAX
2 − 12P
5 + 24P
UNIT
ns
ns
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