SMJ320C6414 Datasheet, PDF (67/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
clock PLL
Most of the internal C64x DSP clocks are generated from a single source through the CLKIN pin. This source
clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5
shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes.
To minimize the clock jitter, a single clean power supply should power both the C64x DSP device and the
external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input
clock timing requirements, see the input and output clocks electrical section.
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source
must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended
ranges of supply voltage and operating case temperature table and the input and output clocks electrical
section). Table 31 lists some examples of compatible CLKIN external clock sources:
Table 31. Compatible CLKIN External Clock Sources
COMPATIBLE PARTS FOR
EXTERNAL CLOCK SOURCES (CLKIN)
Oscillators
PLL
PART NUMBER
JITO-2
STA series, ST4100 series
SG-636
342
ICS525-02
MANUFACTURER
Fox Electronix
SaRonix Corporation
Epson America
Corning Frequency Control
Integrated Circuit Systems
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