SMJ320C6414 Datasheet, PDF (19/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

peripheral register descriptions (continued)
SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Table 10. Interrupt Selector Registers
HEX ADDRESS RANGE
019C 0000
019C 0004
019C 0008
019C 000C − 019C 01FF
ACRONYM
MUXH
REGISTER NAME
Interrupt multiplexer high
MUXL
Interrupt multiplexer low
EXTPOL
−
External interrupt polarity
Reserved
COMMENTS
Selects which interrupts drive CPU
interrupts 10−15 (INT10−INT15)
Selects which interrupts drive CPU
interrupts 4−9 (INT04−INT09)
Sets the polarity of the external
interrupts (EXT_INT4−EXT_INT7)
Table 11. McBSP 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
018C 0000
DRR0
McBSP0 data receive register via Configuration Bus
0x3000 0000 − 0x33FF FFFF
018C 0004
0x3000 0000 − 0x33FF FFFF
018C 0008
018C 000C
018C 0010
018C 0014
018C 0018
018C 001C
018C 0020
018C 0024
018C 0028
018C 002C
018C 0030
018C 0034
018C 0038
018C 003C
018C 0040 − 018F FFFF
DRR0
DXR0
DXR0
SPCR0
RCR0
XCR0
SRGR0
MCR0
RCERE00
XCERE00
PCR0
RCERE10
XCERE10
RCERE20
XCERE20
RCERE30
XCERE30
–
McBSP0 data receive register via Peripheral Bus
McBSP0 data transmit register via Configuration Bus
McBSP0 data transmit register via Peripheral Bus
McBSP0 serial port control register
McBSP0 receive control register
McBSP0 transmit control register
McBSP0 sample rate generator register
McBSP0 multichannel control register
McBSP0 enhanced receive channel enable register 0
McBSP0 enhanced transmit channel enable register 0
McBSP0 pin control register
McBSP0 enhanced receive channel enable register 1
McBSP0 enhanced transmit channel enable register 1
McBSP0 enhanced receive channel enable register 2
McBSP0 enhanced transmit channel enable register 2
McBSP0 enhanced receive channel enable register 3
McBSP0 enhanced transmit channel enable register 3
Reserved
COMMENTS
The CPU and EDMA controller
can only read this register;
they cannot write to it.
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