SMJ320C6414 Datasheet, PDF (115/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415 AND C6416 ONLY]
(CONTINUED)
timing requirements for serial EEPROM interface (see Figure 50)
NO.
8 tsu(DIV-CLKH)
Setup time, XSP_DI valid before XSP_CLK high
9 th(CLKH-DIV)
Hold time, XSP_DI valid after XSP_CLK high
*This parameter is not production tested.
MIN MAX UNIT
50*
ns
0*
ns
switching characteristics over recommended operating conditions for serial EEPROM interface^†
(see Figure 50)
NO.
PARAMETER
1 tw(CSL)
2 td(CLKL-CSL)
Pulse duration, XSP_CS low
Delay time, XSP_CLK low to XSP_CS low
3 td(CSH-CLKH)
Delay time, XSP_CS high to XSP_CLK high
4 tw(CLKH)
Pulse duration, XSP_CLK high
5 tw(CLKL)
Pulse duration, XSP_CLK low
6 tosu(DOV-CLKH) Output setup time, XSP_DO valid after XSP_CLK high
7 toh(CLKH-DOV)
Output hold time, XSP_DO valid after XSP_CLK high
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
2
XSP_CS
3
4
5
XSP_CLK
XSP_DO
XSP_DI
6
7
9
8
MIN TYP MAX UNIT
4092P
ns
0
ns
2046P
ns
2046P
ns
2046P
ns
2046P
ns
2046P
ns
1
Figure 50. PCI Serial EEPROM Interface Timing
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
115