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SMJ320C6414 Datasheet, PDF (100/133 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS | |||
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SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDÄPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A â JANUARY 2004 â REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
REFR
ECLKOUTx
CEx
ABE[7:0] or BBE[1:0]
AEA[22:14, 12:3] or
BEA[20:12, 10:1]
1
1
AEA13 or BEA11
AED[63:0] or BED[15:0]
AOE/SDRAS/SOEâ¡
ARE/SDCAS/SADS/SREâ¡
12
12
8
8
AWE/SDWE/SWEâ¡
â These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an âAâ and all EMIFB signals are prefixed by a
âBâ. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix âAâ or âBâ may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
â¡ ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 32. SDRAM REFR Command for EMIFA and EMIFBâ
100
⢠POST OFFICE BOX 1443 HOUSTON, TEXAS 77251â1443
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