NSC800 Datasheet, PDF (9/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

6 0 Pin Descriptions (Continued)
Status (SO S1) Bus status outputs provide encoded infor-
mation regarding the current M cycle as follows
Machine Cycle
Status
Control
S0 S1 IO M RD WR
Opcode Fetch
11
0
01
Memory Read
01
0
01
Memory Write
10
0
10
I O Read
01
1
01
I O Write
10
1
10
Halt
00
0
01
Internal Operation
01
0
11
Acknowledge of Int
11
0
11
ALE is not suppressed in this cycle
This is the cycle that occurs immediately after the CPU accepts an inter-
rupt (RSTA RSTB RSTC INTR NMI)
Note 1 During halt CPU continues to do dummy opcode fetch from location
following the halt instruction with a halt status This is so CPU can continue
to do its dynamic RAM refresh
Note 2 No early status is provided for interrupt or hardware restarts
6 3 INPUT OUTPUT SIGNALS
Multiplexed Address Data AD(0 – 7) Active high
At RD Time Input data to CPU
At WR Time Output data from CPU
At Falling Edge Least significant byte of address
of ALE Time during memory reference cycle 8-bit
port address during I O reference
cycle
During BREQ High impedance
BACK Cycle
7 0 Connection Diagrams
Dual-In-Line Package
Chip Carrier Package
Top View
TL C 5171–10
Order Number NSC800D or N
See NS Package D40C or N40A
Top View
TL C 5171 – 11
Order Number NSC800E or V
See NS Package E44B or V44A
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