NSC800 Datasheet, PDF (15/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

9 0 Timing and Control
9 1 INTERNAL CLOCK GENERATOR
An inverter oscillator contained on the NSC800 chip pro-
vides all necessary timing signals The chip operation fre-
quency is equal to one half of the frequency of this oscilla-
tor
The oscillator frequency can be controlled by one of the
following methods
1 Leaving the X_OUT pin unterminated and driving the X_IN
pin with an externally generated clock as shown in Figure
6 When driving X_IN with a square wave the minimum
duty cycle is 30% high
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FIGURE 6 Use of External Clock
2 Connecting a crystal with the proper biasing network be-
tween X_IN and X_OUT as shown in Figure 7 Recommend-
ed crystal is a parallel resonance AT cut crystal
Note 1 If the crystal frequency is between 1 MHz and 2 MHz a series
resistor R_S (470X to 1500X) should be connected between
X_OUT and R XTAL and C_Z Additionally the capacitance of C1
and C2 should be increased by 2 to 3 times the recommended
value For crystal frequencies less than 1 MHz higher values of
C1 and C2 may be required Crystal parameters will also affect
the capacitive loading requirements
f(XTAL)
2 MHz k
2
Re1 MX
C1e20 pF
C2e34 pF
(Recommended)
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FIGURE 7 Use Of Crystal
The CPU has a minimum clock frequency input ( X_IN) of
300 kHz which results in 150 kHz system clock speed All
registers internal to the chip are static however there is
dynamic logic which limits the minimum clock speed The
input clock can be stopped without fear of losing any data or
damaging the part You stop it in the phase of the clock that
has X_IN low and CLK OUT high When restarting the CPU
precautions must be taken so that the input clock meets
these minimum specification Once started the CPU will
continue operation from the same location at which it was
stopped During DC operation of the CPU typical current
drain will be 2 mA This current drain can be reduced by
placing the CPU in a wait state during an opcode fetch cycle
then stopping the clock For clock stop circuit see Figure 8
FIGURE 8 Clock Stop Circuit
15
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