NSC800 Datasheet, PDF (51/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 11 Memory Block Moves and Searches (Continued)
76543210
CPIR
11101101
10101001
Compare data in memory location (HL) to the Accumulator
increment the memory decrement the byte counter BC and
repeat until BC e 0 or (HL) equals A
Timing
Addressing Mode
M cycles 4
T states 16 (4 4 3 5)
Register Indirect
REPEAT OPERATIONS
LDIR
Move data from memory location (HL) to memory location
(DE) increment memory pointers decrement byte counter
BC and repeat until BC e 0
A b (HL)
HL w HL a 1
BC w BC b 1
Repeat until BC e 0
or A e (HL)
S Set if sign of subtraction per-
formed for comparison is nega-
tive
Z Set if A e (HL) otherwise reset
H Set according to borrow from
bit 4
P V Set if BC b 1 ⁱ 0 otherwise
reset
N Set
w (DE)
(HL)
DE w DE a 1
SNA
ZNA
CNA
76543210
HL w HL a 1
BC w BC b 1
Repeat until
H Reset
P V Reset
N Reset
11101101
10110001
BC e 0
CNA
Timing For BC ⁱ 0 M cycles 5
76543210
T states 21 (4 4 3 5 5)
11101101
10110000
For BC e 0
Addressing Mode
M cycles 4
T states 16 (4 4 3 5)
Register Indirect
Timing
For BC ⁱ 0 M cycles 5
T states 21 (4 4 3 5 5)
(Note that each repeat is accomplished by a decrement of
the PC so that refresh etc continues for each cycle )
For BCe0 M cycles 4
CPDR
T states 16 (4 4 3 5)
Addressing Mode
Register Indirect
(Note that each repeat is accomplished by a decrement of
the BC so that refresh etc continues for each cycle )
LDDR
Move data from memory location (HL) to memory location
(DE) decrement memory pointers and byte counter BC and
repeat until BC e 0
w (DE)
(HL)
SNA
DE w DE b 1
ZNA
HL w HL b 1
BC w BC b 1
H Reset
P V Reset
Repeat until
N Reset
BC e 0
CNA
76543210
Compare data in memory location (HL) to the contents of
the Accumulator decrement the memory pointer and byte
counter BC and repeat until BC e 0 or until (HL) equals
the Accumulator
A b (HL)
HL w HL b 1
BC w BC b 1
Repeat until BC e 0
or A e (HL)
S Set if sign of subtraction per-
formed for comparison is nega-
tive
Z Set according to equality of A
and (HL) set if true
H Set according to borrow from
bit 4
P V Set if BC b 1 ⁱ 0 otherwise
reset
N Set
CNA
76543210
11101101
11101101
10111000
Timing For BC ⁱ 0 M cycles 5
T states 21 (4 4 3 5 5)
For BCe0 M cycles 4
T states 16 (4 4 3 5)
Addressing Mode
Register Indirect
(Note that each repeat is accomplished by a decrement of
the BC so that refresh etc continues for each cycle )
10111001
Timing For BC ⁱ 0 M cycles 5
T states 21 (4 4 3 5 5)
For BC e 0 M cycles 4
T states 16 (4 4 3 5)
Addressing Mode
Register Indirect
(Note that each repeat is accomplished by a decrement of
the BC so that refresh etc continues for each cycle )
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