NSC800 Datasheet, PDF (19/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

9 0 Timing and Control (Continued)
9 3 INITIALIZATION
RESET IN initializes the NSC800 RESET OUT initializes the
peripheral components The Schmitt trigger at the RESET
IN input facilitates using an R-C network reset scheme dur-
ing power up (see Figure 12 )
To ensure proper power-up conditions for the NSC800 the
following power-up and initialization procedure is recom-
mended
1 Apply power (V_CC and GND) and set RESET IN active
(low) Allow sufficient time (approximately 30 ms if a crys-
tal is used) for the oscillator and internal clocks to stabi-
lize RESET IN must remain low for at least 3t state (CLK)
times RESET OUT goes high as soon as the active
RESET IN signal is clocked into the first flip-flop after the
on-chip Schmitt trigger RESET OUT signal is available to
reset the peripherals
2 Set RESET IN high RESET OUT then goes low as the
inactive RESET IN signal is clocked into the first flip-flop
after the on-chip Schmitt trigger Following this the CPU
initiates the first opcode fetch cycle
Note The NSC800 initialization includes Clear PC to
X’0000 (the first opcode fetch therefore is from memory
location X’0000) Clear registers I (Interrupt Vector Base)
and R (Refresh Counter) to X’00 Clear interrupt control reg-
ister bits IEA IEB and IEC The interrupt control bit IEI is set
to 1 to maintain INS8080A Z80A compatibility (see INTER-
RUPTS for more details) The CPU disables maskable inter-
rupts and enters INTR Mode 0 While RESET IN is active
(low) the A(8–15) and AD(0–7) lines go to high impedance
(TRI-STATE) and all CPU strobes go to the inactive state
(see Figure 13 )
TL C 5171 – 21
FIGURE 12 Power-On Reset
9 4 POWER-SAVE FEATURE
The NSC800 provides a unique power-save mode by the
means of the PS pin PS input is sampled at the last t state
of the last M cycle of an instruction After recognizing an
active (low) level on PS The NSC800 stops its internal
clocks thereby reducing its power dissipation to one half of
operating power yet maintaining all register values and in-
ternal control status The NSC800 keeps its oscillator run-
ning and makes the CLK signal available to the system
When in power-save the ALE strobe will be stopped high
and the address lines AD(0 – 7) A(8 – 15) will indicate the
next machine address When PS returns high the opcode
fetch (or M1 cycle) of the CPU begins in a normal manner
Note this M1 cycle could also be an interrupt acknowledge
cycle if the NSC800 was interrupted simultaneously with PS
(i e PS has priority over a simultaneously occurring inter-
rupt) However interrupts are not accepted during power
save Figure 14 illustrates the power save timing
FIGURE 13 NSC800 Signals During Power-On and Manual Reset
TL C 5171 – 74
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