NSC800 Datasheet, PDF (45/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 8 Bit Set Reset and Test (Continued)
BIT B m₁
Bit b in memory location m₁ is tested via the Z flag
w Z
m_1b
S Undefined
Z Inverse of tested bit
H Set
P V Undefined
N Reset
CNA
76543210
1 1 0 0 1 0 1 1 BIT b (HL)
01
b
110
Timing
M cycles 3
T states 12 (4 4 4)
Addressing Mode
Bit Register Indirect
76 5 43210
1 1 N_X 1 1 1 0 1
BIT b (IXad) (for N_Xe0)
BIT b (IYad) (for N_Xe1)
11 0 01011
d
01
b
110
Timing
Addressing Mode
M cycles 5
T states 20 (4 4 3 5 4)
Bit Indexed
12 9 Rotate and Shift
REGISTER
RLC r
Rotate register r left circular
TL C 5171 – 57
S Set if result is negative
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
C Set according to bit 7 of r
76543210
1 1 0 0 1 0 1 1 RLC r
00000
Timing
Addressing Mode
r (Note alternate for
A register below)
M cycles
T states
Register
2
8 (4 4)
76543210
0 0 0 0 0 1 1 1 RLCA
Timing
M cycles 1
T states 4
Addressing Mode
Implied
(Note RLCA does not affect S Z or P V flags )
RL r
Rotate register r left through carry
TL C 5171 – 58
S Set if result is negative
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
C Set according to bit 7 of r
76543210
1 1 0 0 1 0 1 1 RL r
00010
r
(Note alternate for
A register below)
Timing
M cycles
T states
Addressing Mode
Register
76543210
2
8 (4 4)
0 0 0 1 0 1 1 1 RLA
Timing
M cycles 1
T states 4
Addressing Mode
Implied
(Note RLA does not affect S Z or P V flags )
RRC r
Rotate register r right circular
TL C 5171 – 59
S Set if result is negative
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
C Set according to bit 0 of r
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