NSC800 Datasheet, PDF (17/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

9 0 Timing and Control (Continued)
During the opcode fetch the CPU places the contents of
the PC on the address bus The falling edge of ALE indi-
cates a valid address on the AD(0–7) lines The WAIT input
is sampled during t₂ and if active causes the NSC800 to
insert a wait state (t_w) WAIT is sampled again during t_w so
that when it goes inactive the CPU continues its opcode
fetch by latching in the data on the rising edge of RD from
the AD(0 – 7) lines During t₃ RFSH goes active and AD(0 –
7) has the dynamic RAM refresh address from register R
and A(8 – 15) the interrupt vector from register I
FIGURE 10a Memory Read Write Cycles without WAIT States
TL C 5171 – 17
FIGURE 10b Memory Read and Write with WAIT States
TL C 5171 – 18
17