NSC800 Datasheet, PDF (48/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 9 Rotate and Shift (Continued)
RR m₁
Rotate the data in memory location m₁ right through the
carry
76 5 43210
1 1 N_X 1 1 1 0 1
11 0 01011
SLA (IX a d) (for N_X e 0)
SLA (IY a d) (for N_X e 1)
d
TL C 5171–67
S Set if result is negative
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
C Set according to bit 0 of m₁
76543210
11001011
RR (HL)
00011110
Timing
M cycles 4
T states 15 (4 4 4 3)
Addressing Mode
Register Indirect
76 5 43210
1 1 N_X 1 1 1 0 1
RR (IX a d) (for N_X e 0)
RR (IY a d) (for N_X e 1)
11 0 01011
d
00 0 11110
Timing
Addressing Mode
M cycles
T states
Indexed
6
23 (4 4 3 5 4 3)
SLA m₁
Shift the data in memory location m₁ left arithmetic
00 1 00110
Timing
Addressing Mode
M cycles
T states
Indexed
6
23 (4 4 3 5 4 3)
SRA m₁
Shift the data in memory location m₁ right arithmetic
S Set if result is negative
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
C Set according to bit 0 of m₁
76543210
11001011
SRA (HL)
TL C 5171 – 69
00101110
Timing
M cycles 4
T states 15 (4 4 4 3)
Addressing Mode
Register Indirect
76 5 43210
1 1 N_X 1 1 1 0 1
SRA (IX a d) (for N_X e 0)
SRA (IY a d) (for N_X e 1)
11 0 01011
d
TL C 5171–68
S Set if result is negative
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
C Set according to bit 7 of m₁
76543210
11001011
SLA (HL)
00 1 01110
Timing
Addressing Mode
M cycles
T states
Indexed
6
23 (4 4 3 5 4 3)
SRL m₁
Shift right logical the data in memory location m₁
TL C 5171 – 70
00100110
Timing
Addressing Mode
M cycles 4
T states 15 (4 4 4 3)
Register Indirect
48
S Reset
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
C Set according to bit 0 of m₁