NSC800 Datasheet, PDF (18/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

9 0 Timing and Control (Continued)
Figure 10 shows the timing for memory read (other than
opcode fetchs) and write cycles with and without a wait
t
state The RD stobe is widened by (half the machine
2
state) for memory reads so that the actual latching of the
input data occurs later
Figure 11 shows the timing for input and output cycles with
and without wait states The CPU automatically inserts one
wait state into each I O instruction to allow sufficient time
for an I O port to decode the address
FIGURE 11a Input and Output Cycles without WAIT States
TL C 5171 – 19
WAIT state automatically inserted during IO operation
FIGURE 11b Input and Output Cycles with WAIT States
18
TL C 5171 – 20