NSC800 Datasheet, PDF (13/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

8 0 Functional Description (Continued)
8 4 3 Carry (C)
A carry from the highest order bit of the accumulator during
an add instruction or a borrow generated during a subtrac-
tion instruction sets the carry flag Specific shift and rotate
instructions also affect this bit
Two specific instructions in the NSC800 instruction reper-
toire set (SCF) or complement (CCF) the carry flag
Other operations that affect the C flag are as follows
 Adds
 Subtracts
 Logic Operations (always resets C flag)
 Rotate Accumulator
 Rotate and Shifts
 Decimal Adjust
 Negation of Accumulator
Other operations do not affect the C flag
8 4 4 Adds Subtract (N)
This flag is used in conjunction with the H flag to ensure that
the proper BCD correction algorithm is used during the deci-
mal adjust instruction (DAA) The correction algorithm de-
pends on whether an add or subtract was previously done
with BCD operands
The operations that set the N flag are
 Subtractions
 Decrements (8-bit)
 Complementing of the Accumulator
 Block I O
 Block Searches
 Negation of the Accumulator
The operations that reset the N flag are
 Adds
 Increments
 Logic Operations
 Rotates
 Set and Complement Carry
 Input Register Indirect
 Block Transfers
 Load of the I or R Registers
 Bit Tests
Other operations do not affect the N flag
8 4 5 Parity Overflow (P V)
The Parity Overflow flag is a dual-purpose flag that indi-
cates results of logic and arithmetic operations In logic op-
erations the P V flag indicates the parity of the result the
flag is set (high) if the result is even reset (low) if the result
is odd In arithmetic operations it represents an overflow
condition when the result interpreted as signed two’s com-
plement arithmetic is out of range for the eight-bit accumu-
lator (i e b128 to a127)
The following operations affect the P V flag according to
the parity of the result of the operation
 Logic Operations
 Rotate and Shift
 Rotate Digits
 Decimal Adjust
 Input Register Indirect
The following operations affect the P V flag according to
the overflow result of the operation
 Adds (16 bit with carry 8-bit with without carry)
 Subtracts (16 bit with carry 8-bit with without carry)
 Increments and Decrements
 Negation of Accumulator
The P V flag has no significance immediately after the fol-
lowing operations
 Block I O
 Bit Tests
In block transfers and compares the P V flag indicates the
status of the BC register always ending in the reset state
after an auto repeat of a block move Other operations do
not affect the P V flag
8 4 6 Half Carry (H)
This flag indicates a BCD carry or borrow result from the
low-order four bits of operation It can be used to correct the
results of a previously packed decimal add or subtract op-
eration by use of the Decimal Adjust Instruction (DAA)
The following operations affect the H flag
 Adds (8-bit)
 Subtracts (8-bit)
 Increments and Decrements
 Decimal Adjust
 Negation of Accumulator
 Always Set by Logic AND
Complement Accumulator
Bit Testing
 Always Reset By Logic OR’s and XOR’s
Rotates and Shifts
Set Carry
Input Register Indirect
Block Transfers
Loads of I and R Registers
The H flag has no significance immediately after the follow-
ing operations
 16-bit Adds with without carry
 16-Bit Subtracts with carry
 Complement of the carry
 Block I O
 Block Searches
Other operations do not affect the H flag
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