NSC800 Datasheet, PDF (24/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

9 0 Timing and Control (Continued)
so that the complete state of the CPU just prior to the non-
maskable interrupt may be restored The method of restor-
ing the status of IFF₁ is through the execution of a Return
Non-Maskable Interrupt (RETN) instruction Since this in-
struction indicates that the non-maskable interrupt service
routine is completed the contents of IFF₂ are now copied
back into IFF₁ so that the status of IFF₁ just prior to the
acceptance of the non-maskable interrupt will be automati-
cally restored
Figure 19 depicts the status of the flip flops during a sample
series of interrupt instructions
Interrupt Control Register The interrupt control register
(ICR) is a 4-bit write only register that provides the program-
mer with a second level of maskable control over the four
maskable interrupt inputs
The ICR is internal to the NSC800 CPU but is addressed
through the I O space at I O address port X’BB Each bit in
the register controls a mask bit dedicated to each maskable
interrupt RSTA RSTB RSTC and INTR For an interrupt
request to be accepted on any of these inputs the corre-
sponding mask bit in the ICR must be set (e 1) and IFF₁
and IFF₂ must be set This provides the programmer with
control over individual interrupt inputs rather than just a sys-
tem wide enable or disable
TL C 5171–26
Bit
Name
Function
0
IEI
Interrupt Enable for INTR
1
IEC
Interrupt Enable for RSTC
2
IEB
Interrupt Enable for RSTB
3
IEA
Interrupt Enable for RSTA
For example In order to enable RSTB CPU interrupts must
be enabled and IEB must be set
At reset IEI bit is set and other mask bits IEA IEB IEC are
cleared This maintains the software compatibility between
NSC800 and Z80A
Execution of an I O block move instruction will not affect
the state of the interrupt control bits The only two instruc-
tions that will modify this write only register are OUT (C) r
and OUT (N) A
Operation
Initialize



EI



INTR



EI
RET



NMI



RETN

INTR



NMI



RETN



EI
RET



IFF₁
0
1
0
1
1
0
1
0
0
0
1
1
IFF₂
0
1
0
1
1
1
1
0
0
0
1
1
Comment
Interrupt Disabled
Interrupt Enabled after
next instruction
Interrupt Disable and INTR
Being Serviced
Interrupt Enabled after
next instruction
Interrupt Enabled
Interrupt Disabled
Interrupt Enabled
Interrupt Disabled
Interrupt Disabled and NMI
Being Serviced
Interrupt Disabled and INTR
Being Serviced
Interrupt Enabled after
next instruction
Interrupt Enabled
FIGURE 19 IFF₁ and IFF₂ States Immediately after the
Operation has been Completed
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