NSC800 Datasheet, PDF(41/76 Page) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

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NSC800 Datasheet, PDF (41/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

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12 6 8-Bit Arithmetic (Continued)

76543210

1 0 0 1 0 1 1 0 SUB (HL)

Timing

M cycles 2

T states 7 (4 3)

Addressing Mode

Source Register Indirect

Destination Implied

76 5 43210

1 1 NX 1 1 1 0 1

SUB (IX a d) (for NXe0)

SUB (IY a d) (for NXe1)

10 0 10110

Timing

Addressing Mode

M cycles 5

T states 19 (4 4 3 5 3)

Source Indexed

Destination Implied

SBC A m1

Subtract with carry the contents of memory location m1

from the Accumulator

w A

A b m1 b CY S Set if result is negative

Z Set if result is zero

H Set if carry from bit 3

P V Set if result exceeds 8-bit 2âs

complement range

N Set

C Set according to borrow

condition

76543210

1 0 0 1 1 1 1 0 SBC A (HL)

Timing

M cycles 2

T states 7 (4 3)

Addressing Mode

Source Register Indirect

Destination Implied

76 5 43210

1 1 NX 1 1 1 0 1

SBC A (IX a d) (for NXe0)

SBC A (IY a d) (for NXe1)

10 0 11110

Timing

Addressing Mode

M cycles 5

T states 19 (4 4 3 5 3)

Source Indexed

Destination Implied

AND m1

The data in memory location m1 is logically ANDâed to the

Accumulator

A w A m1

S Set if result is negative

Z Set if result is zero

H Set

P V Set if result parity is even

N Reset

C Reset

76543210

1 0 1 0 0 1 1 0 AND (HL)

Timing

M cycles 2

T states 7 (4 3)

Addressing Mode

Source Register Indirect

Destination Implied

76 5 43210

1 1 NX 1 1 1 0 1

AND (IX a d) (for NXe0)

AND (IY a d) (for NXe1)

10 1 00110

Timing

Addressing Mode

M cycles 5

T states 19 (4 4 3 5 3)

Source Indexed

Destination Implied

OR m1

The data in memory location m1 is logically ORâed with the

Accumulator

A w A m1

S Set if result is negative

Z Set if result is zero

H Reset

P V Set if result parity is even

N Reset

C Reset

76543210

1 0 1 1 0 1 1 0 OR (HL)

Timing

M cycles 2

T states 7 (4 3)

Addressing Mode

Source Register Indexed

Destination Implied

76 5 43210

1 1 NX 1 1 1 0 1

OR (IX a d) (for NXe0)

OR (IY a d) (for NXe1)

10 1 10110

Timing

Addressing Mode

M cycles 5

T states 19 (4 4 3 5 3)

Source Indexed

Destination Implied

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