NSC800 Datasheet, PDF (42/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 6 8-Bit Arithmetic (Continued)
XOR m₁
The data in memory location m₁ is exclusively OR’ed with
the data in the Accumulator
w A
A Z m₁
S Set if result is negative
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
C Reset
76543210
1 0 1 0 1 1 1 0 XOR (HL)
Timing
M cycles 2
T states 7 (4 3)
Addressing Mode
Source Register Indexed
Destination Implied
76 5 43210
1 1 N_X 1 1 1 0 1
XOR (IX a d) (for N_Xe0)
XOR (IY a d) (for N_Xe1)
10 1 01110
d
Timing
Addressing Mode
M cycles 5
T states 19 (4 4 3 5 3)
Source Indexed
Destination Implied
CP m₁
Compare the data in memory location m₁ with the data in
the Accumulator via subtraction
A b m₁
S Set if result is negative
Z Set if result is zero
H Set if borrow from bit 4
P V Set if result exceeds 8-bit 2’s
complement range
N Set
C Set according to borrow
condition
76543210
1 0 1 1 1 1 1 0 CP (HL)
Timing
M cycles 2
T states 7 (4 3)
Addressing Mode
Source Register Indirect
Destination Implied
76 5 43210
1 1 N_X 1 1 1 0 1
CP (IX a d) (for N_Xe0)
CP (IY a d) (for N_Xe1)
10 1 11110
d
Timing
Addressing Mode
M cycles 5
T states 19 (4 4 3 5 3)
Source Indexed
Destination Implied
INC m₁
Increment data in memory location m₁
w m₁
m₁ a 1
S Set if result is negative
Z Set if result is zero
H Set according to carry from bit
3
P V Set if data was X’7F before op-
eration
N Reset
CNA
76543210
0 0 1 1 0 1 0 0 INC (HL)
Timing
M cycles 3
T states 11 (4 4 3)
Addressing Mode
Source Register Indexed
Destination Register Indexed
76 5 43210
1 1 N_X 1 1 1 0 1
INC (IX a d) (for N_Xe0)
INC (IY a d) (for N_Xe1)
00 1 10100
d
Timing
Addressing Mode
M cycles 6
T states 23 (4 4 3 5 4 3)
Source Indexed
Destination Indexed
DEC m₁
Decrement data in memory location m₁
w m₁
m₁ b 1
S Set if result is negative
Z Set if result is zero
H Set according to borrow from
bit 4
P V Set only if m₁ was X’80 before
operation
N Set
CNA
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