NSC800 Datasheet, PDF (49/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 9 Rotate and Shift (Continued)
76543210
11001011
SRL (HL)
00111110
Timing
M cycles 4
T states 15 (4 4 4 3)
Addressing Mode
Register Indirect
76 5 43210
1 1 N_X 1 1 1 0 1
SRL (IX a d) (for N_X e 0)
SRL (IY a d) (for N_X e 1)
11 0 01011
d
00 1 11110
Timing
Addressing Mode
M cycles
T states
Indexed
6
23 (4 4 3 5 4 3)
REGISTER MEMORY
RLD
Rotate digit left and right between the Accumulator and
memory (HL)
TL C 5171 – 71
S Set if result is negative
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
CNA
76543210
11101101
01101111
Timing
Addressing Mode
M cycles 5
T states 18 (4 4 3 4 3)
Implied Register Indirect
RRD
Rotate digit right and left between the Accumulator and
memory (HL)
TL C 5171 – 72
S Set if result is negative
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
CNA
76543210
11101101
01100111
Timing
Addressing Mode
M cycles 5
T states 18 (4 4 3 4 3)
Implied Register Indirect
12 10 Exchanges
REGISTER REGISTER
EX DE HL
Exchange the contents of the 16-bit register pairs DE and
HL
DE
HL
No flags affected
76543210
11101011
Timing
Addressing Mode
M cycles 1
T states 4
Register
EX AF A’F’
The contents of the Accumulator and flag register are ex-
changed with their corresponding alternate registers that is
A and F are exchanged with A’ and F’
A
A’
No flags affected
F
F’
76543210
00001000
Timing
Addressing Mode
M cycles 1
T states 4
Register
49