NSC800 Datasheet, PDF (57/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 14 Program Control (Continued)
RETN
Unconditional return from non-maskable interrupt handling
subroutine Functionally similar to RET instruction except
interrupt enable state is restored to that prior to non-mask-
able interrupt
w PC_L
(SP)
No flags affected
w PC_H
(SP a 1)
SP w SP a 2
w IFF₁
IFF₂
76543210
11101101
01000101
Timing
Addressing Mode
M cycles 4
T states 14 (4 4 3 3)
Register Indirect
RESTARTS
RST P
The present contents of the PC are pushed onto the memo-
ry stack and the PC is loaded with dedicated program loca-
tions as determined by the specific restart executed
w (SP b 1)
PC_H
w (SP b 2)
PC_L
SP w SP b 2
No flags affected
PC_H w 0
PC_L w P
76543210
11
t
111
Timing
Addressing Mode
M cycles 3
T states 11 (5 3 3)
Modified Page Zero
p 00H 08H 10H 18H 20H 28H 30H 38H
t 000 001 010 011 100 101 110 111
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