NSC800 Datasheet, PDF(53/76 Page) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

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NSC800 Datasheet, PDF (53/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

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12 12 Input Output (Continued)

OUT (n) A

Output the Accumulator to the I O device at address n

(n) w A

No flags affected

76543210

11010011

Timing

Addressing Mode

M cycles 3

T states 11 (4 3 4)

Source Register

Destination Direct

OUTD

Data is output from memory location (HL) to the I O device

at port address (C) and the HL memory pointer and byte

counter B are decremented

S Undefined

BwBb1

Z Set if Bb1e0 otherwise reset

HL w HL b 1

H Undefined

P V Undefined

N Set

CNA

76543210

11101101

10101011

Timing

Addressing Mode

M cycles 4

T states 16 (4 5 3 4)

Implied Source Register In-

direct

Destination Register Indirect

INIR

Data is input from the I O device at port address (C) to

memory location (HL) the HL memory pointer is increment-

ed and the byte counter B is decremented The cycle is

repeated until B e 0

(Note that B is tested for zero after it is decremented By

loading B initially with zero 256 data transfers will take

place )

(HL) w (C)

S Undefined

HL w HL a 1

Z Set

BwBb1

H Undefined

Repeat until B e 0 P V Undefined

N Set

CNA

76543210

11101101

10110010

Timing For B i 0

M cycles 5

T states 21 (4 5 3 4 5)

For B e 0

M cycles 4

T states 16 (4 5 3 4)

Addressing Mode

Implied Source Register In-

direct

Destination Register Indirect

(Note that at the end of each data transfer cycle interrupts

may be recognized and two refresh cycles will be per-

formed )

OTIR

Data is output to the I O device at port address (C) from

memory location (HL) the HL memory pointer is increment-

ed and the byte counter B is decremented The cycles are

repeated until B e 0

(Note that B is tested for zero after it is decremented By

loading B initially with zero 256 data transfers will take

place )

S Undefined

HL w HL a 1

H Undefined

BwBb1

Z Set

Repeat until B e 0 P V Undefined

N Set

CNA

76543210

11101101

10110011

Timing For B i 0

M cycles 5

T states 21 (4 5 3 4 5)

For B e 0

M cycles 4

T states 16 (4 5 3 4)

Addressing Mode

Implied Source Register In-

direct

Destination Register Indirect

(Note that at the end of each data transfer cycle interrupts

may be recognized and two refresh cycles will be per-

formed )

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