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NSC800 Datasheet, PDF (4/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor
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4 0 AC Electrical Characteristics VCC e 5V g10% GND e 0V unless otherwise specified
Symbol
Parameter
NSC800-1 NSC800-3 NSC800-35 NSC800-4 Units
Min Max Min Max Min Max Min Max
Notes
tX
Period at XIN and XOUT 500 3333 200 3333 142 3333 125 3333 ns
Pins
T
Period at Clock Output 1000 6667 400 6667 284 6667 250 6667 ns
(e2 tX)
tR
Clock Rise Time
110
110
90
80 ns Measured from
10% – 90% of signal
tF
Clock Fall Time
70
60
55
50 ns Measured from
10% – 90% of signal
tL
Clock Low Time
435
150
90
80
ns 50% duty cycle square
wave input on XIN
tH
Clock High Time
450
145
85
75
ns 50% duty cycle square
wave input on XIN
tACC(OP) ALE to Valid Data
tACC(MR) ALE to Valid Data
1340
490
1875
620
340
300 ns Add t for each WAIT STATE
405
360 ns Add t for each WAIT STATE
tAFR
AD(0 – 7) Float after
RD Falling
0
0
0
0 ns
tBABE
BACK Rising to Bus
Enable
1000
400
300
250 ns
tBABF
BACK Falling to
Bus Float
50
50
50
50 ns
tBACL
BACK Fall to CLK
425
125
60
Falling
55
ns
tBRH
tBRS
tCAF
BREQ Hold Time
BREQ Set-Up Time
Clock Falling ALE
Falling
0
0
0
100
50
50
0 70 0 65
0
0
ns
45
ns
60 0 55 ns
tCAR
Clock Rising to ALE
Rising
0 100 0 100 0
90 0 80 ns
tCRD
Clock Rising to
Read Rising
100
90
90
80 ns
tCRF
Clock Rising to
Refresh Falling
80
70
70
65 ns
tDAI
ALE Falling to INTA
445
160
95
Falling
85
ns
tDAR
ALE Falling to
RD Falling
400 575 160 250 100 180 90 160 ns
tDAW
ALE Falling to
WR Falling
900 1010 350 420 225 300 200 265 ns
tD(BACK)1 ALE Falling to BACK
2460
975
635
Falling
560
ns Add t for each WAIT state
Add t for opcode fetch cycles
tD(BACK)2 BREQ Rising to BACK 500 1610 200 700 140 540 125 475 ns
Rising
tD(I)
ALE Falling to INTR
NMI RSTA-C PS
BREQ Inputs Valid
1360
475
284
250 ns Add t for each WAIT state
Add t for opcode fetch cycles
tDPA
Rising PS to
Falling ALE
500 1685 200 760 140 580 125 510 ns See Figure 14 also
tD(WAIT) ALE Falling to
WAIT Input Valid
OP Opcode Fetch
MR Memory Read
550
250
170
125 ns
4
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