NSC800 Datasheet, PDF (31/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 0 Instruction Set (Continued)
12 2 INSTRUCTION SET MNEMONIC NOTATION
In the following instruction set listing the notations used are
shown below
b Designates one bit in a register or memory location
Bit address mode uses this indicator
cc Designates condition codes used in conditional
Jumps Calls and Return instruction may be
NZ e Non-Zero (Z flage0)
Z e Zero (Z flage1)
NC e Non-Carry (C flage0)
C e Carry (C flage1)
PO e Parity Odd or No Overflow (P Ve0)
PE e Parity Even or Overflow (P Ve1)
P e Positive (Se0)
M e Negative (Se1)
d Designates an 8-bit signed complement displace-
ment Relative or indexed address modes use this
indicator
kk Subset of cc condition codes used in conjunction with
conditional relative jumps may be NZ Z NC or C
m₁ Designates (HL) (IXad) or (IYad) Register indirect
or indexed address modes use this indicator
m₂ Designates (BC) (DE) or (nn) Register indirect or di-
rect address modes use this indicator
n Any 8-bit binary number
nn Any 16-bit binary number
p Designates restart vectors and may be the hex values
0 8 10 18 20 28 30 or 38 Restart instructions
employing the modified page zero addressing mode
use this indicator
pp Designates the BC DE SP or any 16-bit register used
as a destination operand in 16-bit arithmetic opera-
tions employing the register address mode
qq Designates BC DE HL A F IX or IY during opera-
tions employing register address mode
r Designates A B C D E H or L Register addressing
modes use this indicator
rr Designates BC DE HL SP IX or IY Register ad-
dressing modes use this indicator
ss Designates HL IX or IY Register addressing modes
use this indicator
X_L Subscript L indicates the lower-order byte of a 16-bit
register
X_H Subscript H indicates the high-order byte of a 16-bit
register
( ) parentheses indicate the contents are considered a
pointer address to a memory or I O location
12 3 ASSEMBLED OBJECT CODE NOTATION
Register Codes
r Register rp Register rs Register
000
B
00
BC
00
BC
001
C
01
DE
01
DE
010
D
10
HL
10
HL
011
E
11
SP
11
AF
100
H
pp Register qq Register
101
L
00
BC
00
BC
111
A
01
DE
01
DE
10
IX
10
HL
11
SP
11
AF
Conditions Codes
cc
Mnemonic
000
NZ
001
Z
010
NC
011
C
100
PO
101
PE
110
P
111
M
kk
Mnemonic
00
NZ
01
Z
10
NC
11
C
True Flag Condition
Ze0
Ze1
Ce0
Ce1
P Ve0
P Ve1
Se0
Se1
True Flag Condition
Ze0
Ze1
Ce0
Ce1
Restart Addresses
t
T
000
X’00
001
X’08
010
X’10
011
X’18
100
X’20
101
X’28
110
X’30
111
X’38
31