NSC800 Datasheet, PDF (52/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 12 Input Output
IN A (n)
Input data to the Accumulator from the I O device at ad-
dress N
A w (n)
No flags affected
76543210
11011011
n
Timing
Addressing Mode
M cycles 3
T states 11 (4 3 4)
Source Direct
Destination Register
IN r (C)
Input data to register r from the I O device addressed by the
contents of register C If re110 only flags are affected
r w (C)
S Set if result is negative
Z Set if result is zero
H Reset
P V Set if result parity is even
N Reset
CNA
76543210
11101101
01
r
000
Timing
Addressing Mode
M cycles 3
T states 12 (4 4 4)
Source Register Indirect
Destination Register
OUT (C) r
Output register r to the I O device addressed by the con-
tents of register C
(C) w r
No flags affected
76543210
11101101
01
r
001
Timing
Addressing Mode
M cycles 3
T states 12 (4 4 4)
Source Register
Destination Register Indirect
INI
Input data from the I O device addressed by the contents of
register C to the memory location pointed to by the contents
of the HL register The HL pointer is incremented and the
byte counter B is decremented
(HL) w (C)
S Undefined
BwBb1
HL w HL a 1
Z Set if Bb1e0 otherwise reset
H Undefined
P V Undefined
N Set
CNA
76543210
11101101
10100010
Timing
Addressing Mode
M cycles 4
T states 16 (4 5 3 4)
Implied Source Register In-
direct
Destination Register Indirect
OUTI
Output data from memory location (HL) to the I O device at
port address (C) increment the memory pointer and decre-
ment the byte counter B
(C) w (HL)
S Undefined
BwBb1
Z Set if Bb1e0 otherwise reset
HL w HL a 1
H Undefined
P V Undefined
N Set
CNA
76543210
11101101
10100011
Timing
Addressing Mode
M cycles 4
T states 16 (4 5 3 4)
Implied Source Register In-
direct
Destination Register Indirect
IND
Input data from I O device at port address (C) to memory
location (HL) and decrement HL memory pointer and byte
counter B
(HL) w (C)
S Undefined
HL w HL b 1
BwBb1
Z Set if Bb1e0 otherwise reset
H Undefined
P V Undefined
N Set
CNA
76543210
11101101
10101010
Timing
Addressing Mode
M cycles 4
T states 16 (4 5 3 4)
Implied Source Register In-
direct
Destination Register Indirect
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