NSC800 Datasheet, PDF (35/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

12 5 16-Bit Loads (Continued)
PUSH qq
Push the contents of register pair qq onto the memory
stack
w (SP – 1) qq_H
No flags affected
w (SP – 2) qq_L
SP w SP b 2
7 6 5 4 3 2 1 0 PUSH BC
1 1 rs 0 1 0 1 ^{PUSH DE}
PUSH HL
PUSH AF
Timing
M cycles 3
T states 11 (5 3 3)
Addressing Mode
Source Register
Destination Register Indirect
(Stack)
76 5 43210
1 1 N_X 1 1 1 0 1
PUSH IX (for N_Xe0)
PUSH IY (for N_Xe1)
11 1 00101
Timing
Addressing Mode
M cycles 3
T states 15 (4 5 3 3)
Source Register
Destination Register Indirect
(Stack)
MEMORY TO REGISTER
LD rr (nn)
Load 16-bit register from memory location nn
w rr_L
(nn)
No flags affected
w rr_H
(nn a 1)
76543210
LD HL (nn)
0 0 1 0 1 0 1 0 _{(note an alternate}
n (low-order byte)
opcode below)
n (high-order byte)
Timing
Addressing Mode
M cycles 5
T states 16 (4 3 3 3 3)
Source Direct
Destination Register
76543210
11101101
0 1 rp 0 0 1 1
LD BC (nn)
LD DE (nn)
LD HL (nn)
LD SP (nn)
n (low-order byte)
n (high-order byte)
Timing
M cycles 6
T states 20 (4 4 3 3 3 3)
Addressing Mode
Source Direct
Destination Register
76 5 43210
1 1 N_X 1 1 1 0 1
LD IX (nn)(for N_X e 0)
LD IY (nn) (for N_X e 1)
00 1 01010
n (low-order byte)
n (high-order byte)
Timing
Addressing Mode
M cycles 6
T states 20 (4 4 3 3 3 3)
Source Direct
Destination Register
POP qq
Pop the contents of the memory stack to register qq
w qq_L
(SP)
No flags affected
w qq_H
(SP a 1)
SP w SP a 2
7 6 5 4 3 2 1 0 POP BC
1 1 rs 0 0 0 1 ^{POP DE}
POP HL
POP AF
Timing
M cycles 3
T states 10 (4 3 3)
Addressing Mode
Source Register Indirect
(Stack)
Destination Register
76 5 43210
1 1 N_X 1 1 1 0 1
POP IX (for N_Xe0)
POP IY (for N_Xe1)
11 1 00001
Timing
Addressing Mode
M cycles 4
T states 14 (4 4 3 3)
Source Register Indirect
(Stack)
Destination Register
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