NSC800 Datasheet, PDF(43/76 Page) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

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NSC800 Datasheet, PDF (43/76 Pages) National Semiconductor (TI) – NSC800TM High-Performance Low-Power CMOS Microprocessor

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12 6 8-Bit Arithmetic (Continued)

76543210

0 0 1 1 0 1 0 1 DEC (HL)

Timing

M cycles 3

T states 11 (4 4 3)

Addressing Mode

Source Register Indexed

Destination

dexed

76 5 43210

1 1 NX 1 1 1 0 1

DEC (IX a d) (for NX e 0)

DEC (IY a d) (for NX e 1)

00 1 10101

Timing

Addressing Mode

M cycles 6

T states 23 (4 4 3 5 4 3)

Source Indexed

Destination Indexed

12 7 16-Bit Arithmetic

ADD ss pp

Add the contents of the 16-bit register rp or pp to the con-

tents of the 16-bit register ss

w ss ss a rp S N A

ZNA

w ss ss a pp H Set if carry from bit 11

PVNA

N Reset

C Set if carry from bit 15

76543210

0 0 rp 1 0 0 1 ADD HL rp

Timing

Addressing Mode

76 5 43

1 1 NX 1 1

M cycles 3

T states 11 (4 4 3)

Source Register

Destination Register

210

101

ADD IX pp (for NX e 0)

ADD IY pp (for NX e 1)

0 0 pp 1 0 0 1

Timing

Addressing Mode

M cycles 4

T states 15 (4 4 4 3)

Source Register

Destination Register

ADC HL pp

The contents of the 16-bit register pp are added with the

carry bit to the HL register

w HL

HL a pp a CY

S Set if result is negative

Z Set if result is zero

H Set according to carry out of bit

P V Set if result exceeds 16-bit 2âs

complement range

N Reset

C Set if carry out of bit 15

76543210

11101101

0 1 pp 1 0 1 0

Timing

Addressing Mode

M cycles 4

T states 15 (4 4 4 3)

Source Register

Destination Register

SBC HL pp

Subtract with carry the contents of the 16-bit pp register

from the 16-bit HL register

w HL

HL b pp b CY

S Set if result is negative

Z Set if result is zero

H Set according to borrow from

bit 12

P V Set if result exceeds 16-bit 2âs

complement range

N Set

C Set according to borrow condi-

tion

76543210

11101101

0 1 pp 0 0 1 0

Timing

Addressing Mode

M cycles 4

T states 15 (4 4 4 3)

Source Register

Destination Register

INC rr

Increment the contents of the 16-bit register rr

rr w rr a 1

No flags affected

7 6 5 4 3 2 1 0 INC BC

0 0 rp 0 0 1 1 INC DE

INC HL

INC SP

Timing

M cycles 1

T states 6

Addressing Mode

76 5 43210

1 1 NX 1 1 1 0 1

INC IX (for NXe0)

INC IY (for NXe1)

00 1 00011

Timing

Addressing Mode

M cycles

T states

10 (4 6)

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